Me postulé en línea. Acudí a una entrevista en Intel Corporation (San Jose, CA) en oct 2018
Entrevista
The interview was based on the fundamentals of VLSI and timing violations. The flow of physical design was asked. How power dissipation happens in CMOS Design. Focus more on Static Time Analysis.
Acudí a una entrevista en Intel Corporation (Petah Tikva)
Entrevista
very nice people. given 2 question one on system of the group and one for coding in binary search and recursion. we started by little talking and then a little bit on one of the project and then 2 questions
Preguntas de entrevista [1]
Pregunta 1
1. given graph and car with light sensor and we want to find the right spot of the dot on the graph. it was binary search classical
Me postulé en línea. Acudí a una entrevista en Intel Corporation (Bengaluru) en may 2026
Entrevista
Deep whiteboard interview , was asked to draw graphs for non ideal characteristics for cmos design and pvt corners. Questions related to project and physical design concepts. Focused on semiconductor physics and technical depth in each answer.
Preguntas de entrevista [1]
Pregunta 1
was asked to draw graphs for non ideal characteristics for cmos design and pvt corners.Questions related to project and physical design concepts. Focused on semiconductor physics and technical depth in each answer.
Acudí a una entrevista en Intel Corporation (Austin, TX)
Entrevista
This was the second round lasted about an hour or so. The first round was mostly about my work as I had 3 year experience and I had to walk them through the projects I did etc..,.
Preguntas de entrevista [1]
Pregunta 1
If the combination logic between 2 FF's is cut like an interface, how do you set_input_delay and set_output_delay for left and right partitions. The clock is the same for both.
