It can be done by two ways Clocked Circuit: Use a one bit adder and a register. Output of the register acts as 2nd input to the adder. Half adder can also be used. Combinational Circuit: We can do it in 4 full adders. For the adders A and B, let 6 bits be the inputs. For adders C, use the 7th bit and Carry of adder A and B. Adder C gives sum as bit 0. For adder D, use carry from all three adders. The sum is bit 1 and carry is bit 2.

For this question you need 2 1-bit full-adder and 1 2-bits full adder. Let's call 7 bits as b0-b6. b0-b2 should be the input of 1-bit FA1 and b3-b5 for FA2. The output from FA1 and FA2 become 2-bits input of FA3 and b6 be the carry-in.

depending on resource and timing constraints, you can use a cascade of adders, where you repeatdly add each bit starting with bit 7 to each other. this is slow because the critical path is on the Cin -> Cout. to improve, you can go further and use a 7bit decoder/any arrangement of decoder/column muxer + decoder for a lookup, which is essentially an SRAM array design to store this value so that next time you try to do this computation, you can directly access it. Essentially caching computation result. This requires extra circuitry overhead, but means you only have to compute the sums once.

4 full adder is a waste, you can do some optimization to achieve the goal by using two full adder. Of course, you need to use some XOR gates, inverter, AND gates, and MUXes

input [6:0]; output sum; always@(input) begin sum = 0; sum = input[0]+input[1]+input[2]+input[3]+input[4]+input[5]+input[6]; end Lets verilog do the synthesis , this is a vaild combinational circuit design!!!