1 Screening Round and 4 Technical rounds and 1 HR Round conducted. In 1 week interview scheduled and offer released in 2 to 3 weeks. Questions from system verilog and uvm, Project related question which have hands on experience

UVM question System Verilog Question AMBA Buses, AXI, AHB and APB When and how would you perform a factory override? Describe the differences between components and objects in UVM. How do you connect a DUT interface to a UVM component? Which UVM phase do you integrate to for phase runs for test cases? How would you reduce the time it takes to initiate a UVM run phase?