Design Verification Engineer
Experience: 2–4 years
Location: Hyderabad , Bengaluru

Responsibilities:
Understand and interpret industry standards/specifications.
Contribute to architecture development and document implementation details.
Perform hands-on work across all phases of the verification cycle.
Ensure compliance with the latest verification methodologies.
Develop and maintain Verification IPs.
Define functional coverage matrix and comprehensive test plans.
Manage regressions and drive functional coverage closure.
Integrate DUT and perform verification for IP delivery sign-off.
Lead small teams and mentor junior engineers.

Required Skills:
Strong verification concepts with hands-on experience in the complete verification cycle.
Proficiency in Verilog, SystemVerilog, and UVM.
Experience in UVM-based Verification IP development.
Knowledge of AMBA AXI/AHB/APB system buses.
Practical exposure to PCIe, Ethernet, USB, or DDR protocols.
Hands-on experience with SystemVerilog Assertions (SVA).
Scripting expertise for automation, release processes, simulations, and regressions.
Strong communication skills (written and oral).

Desirable Skills:
Ability to lead Verification IP development with 2+ junior engineers.
Exposure to the full verification cycle in complex projects.

Work Location: In person