1 screening, 1 coding assessment, final round in person with various 1:1's digital design UVM question. HR moved very quickly and everything was within a month. Friendly staff however the final interview was quite challenging since i did not know about packet protocols.
Preguntas de entrevista [1]
Pregunta 1
screening they asked what asynchronous vs synchronous filp flop
Me postulé en línea. Acudí a una entrevista en SpaceX (Redmond, WA) en nov 2017
Entrevista
Interview process borders on abuse and is clearly designed to get free work out of applicants. I put 35+ hours into a Verilog design problem that would have taken 4 times that to complete. Only to have them come back with factually false claims that they found bugs in my solution that were not actually bugs. I spoke to absolutely no one with any engineering competence whatsover.
Preguntas de entrevista [1]
Pregunta 1
They asked me to complete a complex Verilog design, including testbench covering all conceivable corner cases, and a PowerPoint about it. It was obviously impossible to complete in the time allowed, so clearly part of the interview is to find out who submits to slave labor without complaint. Details of the design question are protected by NDA.