Interview was very in depth and challenging, They require knowledge from RC basics, Semiconductor basics. They mostly test your analysis skills using real time examples. Would advice all aspirants to ramp up their basics knowledge before attending.
Me postulé en línea. Acudí a una entrevista en FrenusTech
Entrevista
1.Resume selection.
2.technical round interview process 1.5 hour
3.Hr round interview 30 min
Q1: What is UVM? What is the advantage of UVM?
Q3. What is the difference between uvm_component and uvm_object?
OR.
We already have uvm_object, why do we need uvm_component which is actually derived class of uvm_object?
Q4: Why phasing is used? What are the different phases in uvm?
Preguntas de entrevista [1]
Pregunta 1
Questions from Sv,UVM,Verilog ,Projects.
Q1: What is UVM? What is the advantage of UVM?
Q3. What is the difference between uvm_component and uvm_object?
OR.
We already have uvm_object, why do we need uvm_component which is actually derived class of uvm_object?
Q4: Why phasing is used? What are the different phases in uvm?
Me postulé en persona. Acudí a una entrevista en FrenusTech en ene 2021
Entrevista
It was good experience. There were two rounds. Written test and face to face interview.
In face to face interview Questions were from digital electronics, SV ,UVM and aptitude and logical reasoning
Preguntas de entrevista [1]
Pregunta 1
Basics of Digital Electronics
UVM & SV
Previous projects i have worked on
