There were total 4 rounds ( 1Written + 3Technical)
Round 1: Written test( 20 aptitude and 20 Technical). Technical questions were mainly from digital circuit design (Gate standard) and aptitude were mainly quants( Time and Work, Time and distance, average, Probability, etc.) Total alloted time was 60 minutes. Shortlisted candidates were taken to the next round.
Round 2: Digital circuit are drawn on paper and was asked to draw the output waveform. Circuit mainly consists of D Flip Flop, Latch, Inverter CMOS etc.
Round 3: Asked to draw and explain Latch, MUX, Counter and other basic circuits using CMOS, TG etc. ASIC Design flow, Full custom and semi custom ASIC Design flow. If you know python then various questions on Python.
Round 4: Asked about Latchup problem in CMOS, Power dissipation in CMOS inverter, Latch using MUX, Full adder using Half adder , Verilog / VHDL code for Latch and Flip Flop, Setup time and hold time ( complete explanation) and remedy, MOS working( Cross sectional view and characteristic curves)
