Applied on LinkedIN and was contacted by the manager in about a week's time. Phone interview was for half an hour and was highly technical. Was informed that there were more candidates under consideration and that I would be contacted by the recruiter if they would like to follow up. To my pleasant surprise, the manager directly e-mailed me instead informing me that they would like to schedule an on-site interview. Recruiter contacted me regarding availability and informed me that I will shortly receive a confirmation of the interview date and a tentative itinerary. However, till the last day prior to the interview I did not receive the confirmation, so I had to frantically contact the recruiter and after a lot of confusion, the interview was confirmed for the following day. The on-site interview was the usual 5 round affair, including the manager and director. It was all technical; neither were HRs involved and nor were there any behavioral type questions. The team seemed nice and seemed to have a lot of people experienced in System Verilog, UVM, Verilog, Perl and the whole shebang. One of the interviewers (let's say interviewer A) had some challenging questions to pose and, seemed to be very particular about the answers and was not interested in my approach. It felt like the result could go either way as I was quite confident about the other rounds. After a tense week of waiting, the manager e-mailed me again informing me that they have it narrowed down to another candidate and me and would like me to come in for a "tie-breaker" interview. Was another 2 rounds of technical interviews, which of course included the interviewer A. After 2 more days the recruiter finally contacted me to inform me that the team would like to extend an offer to me. Communication and negotiations with the recruiter were painfully slow and the only part that left a sour taste in the mouth in what was otherwise a pretty good and professional interview process.

interview had 3 rounds. 1 telephonic and 2 face 2 face interview by senior people and one last round with the manager. the questions were on deep concepts of system verilog..like OOPS, mailboxes, testbench design problems, fork join. there were few logical problems and i was asked to write the algorithm for them.. like algo for finding the largest number in a series. or sorting algorithms, optimized alogorithm. design problem for FIFO depth calculation in case of different read and write rates. FSM problem. i had to write the state machime to find if the number was divisible by 3 or not. sequence detector for divisible by 3 numbers in cummulative manner. how to convert 2x1 mux to 4x1 mux. how to make AND gate OR gate from MUX. unique number sorting algorithms etc.