Verilog question with additional requirements. Design a FSM providing fibonacci sequence with enable and reset. Output should be immediate.

Question

Anónimo · Accepted Answer

Two registers storing last two numbers in sequence with adding circuit muxed  with the enable signal. Combinational output from mux. Answer should be in verilog code.

answer · Answer

This is actually another way of asking: what is the difference of blocking and non blocking assignment. and the key point in this question is to use the non blocking assignment

Cirrus Logic

Pregunta de entrevista de Cirrus Logic

Respuestas de entrevistas

Empresas seguidas

Búsquedas de empleo