One hour and loop with 5 people each round focusing on eache step of physical design flow and cadence tools. I have a thesis on RISC V low voltage pd so they asked about that more

Application via Qualcomm careers or referral. Recruiter may reach out for basic screening: Your background, tools used (ICC2, PrimeTime, RedHawk, etc.) Areas of expertise: floorplanning, CTS, routing, STA, DRC, EMIR, etc. Experience with multi-VDD, ECOs, hierarchical designs, colored flows, etc. Technical Phone Interviews (1–2 rounds) Each round typically lasts 45–60 minutes.